Samsung recently presented its next-generation 2nm semiconductor fabrication process at the SAFE Forum 2026 in South Korea. The company is employing a methodology known as Design Technology Co-Optimization (DTCO), which allows for simultaneous optimization of chip design and manufacturing processes. By collaborating with over 21 partner companies specializing in Electronic Design Automation software and Intellectual Property blocks, Samsung aims to enhance chip size, manufacturing cost, power efficiency, performance, and production yield. The focus is also on improving SRAM, an ultra-fast memory crucial for AI workloads.
At the event, more than 400 representatives from partner companies showcased technologies that aid in chip design for Samsung Foundry’s processes. A notable case study was presented by Rebellion, a South Korean AI accelerator startup, which developed the Rebel100 NPU using Samsung’s 4nm process, achieving significant performance and power efficiency. Samsung is strengthening its partnerships within the AI and high-performance computing sectors and aims to become a central hub for the AI semiconductor ecosystem.
Additionally, Samsung is collaborating with South Korea’s Ministry of Trade, Industry and Energy on initiatives to nurture AI semiconductor talent and support local fabless chip companies through programs like the Multi-Project Wafer initiative.
